t.BA.ET.DT.19HS (Digital Technology) 
Module: Digital Technology
This information was generated on: 19 April 2024
Digital Technology
Organised by


Version: 3.0 start 01 August 2021

Short description

Design of combinational logic circuits with digital gates. Calculating with binary and hexadecimal numbers. Apply adding logic. Creating truth tables and temporal representation of digital signals. Design of sequential circuits and their description in VHDL.

Module coordinator

Gelke, Hans-Joachim (gelk)

Learning objectives (competencies)

Objectives Competences Taxonomy levels
You know and understand simple combinational basic circuits with digital gates, you can interpret a schema and master the realization of simple functions as well as the creation and interpretation of truth tables F, M K2, K3
You can describe digital systems in various logical forms F, M K2, K3
You can calculate with binary and hexadecimal numbers F K2
You know and understand simple adder logic (half adder and full adder) F, M K2
You know and understand simple sequential logic circuits (counters, shift registers, automats) and can analyze and design them F, M K2, K3
You can describe the function of a circuit in the time domain (time history diagrams) F, M K2, K3
You can describe and synthesize simple digital basic circuits textually with VHDL F, M K2, K3, K4
You can visualize a digital circuit with FPGA tools in the time domain   K2, K3, K4

Module contents

● Introduction to digital technology and combinational and sequential logic.
● Number systems (binary, hexadecimal, representation of negative numbers (single, two's complement), arithmetic with negative numbers)
● Logical functions and tags: INV, AND, OR, NAND, NOR, XOR
● Combinational logic: logical operations, combinational logic
● Truth table and combinational basic circuits: Half/full adders, subtractors, multiplexers and demultiplexers, decoders (e.g. BCD => 7-segment).
● Sequential logic: FlipFlops, synchronous circuits, counters, shift registers, introduction Moore Automat
● Introduction to textual hardware description in VHDL (Single Entity and Architecture, Process with combinational and clocked logic)
● Analysis of digital circuits at the time level (signal tap).

Teaching materials

Altera DE-0 lite FPGA Development Board on a loan basis for each Student, such that the Lab Exercises can be done at home

Supplementary literature

Digitaltechnik: Eine Einführung mit VHDL, Jürgen Reinhard


Basics of mathematics, physics and German at vocational baccalaureate level

Teaching language

(X) German ( ) English

Part of International Profile

( ) Yes (X) No

Module structure

Type 1a
  For more details please click on this link: T_CL_Modulauspraegungen_SM2025


Description Type Form Scope Grade Weighting
Graded assignments during teaching semester Quiz multichoice 45 min. grades 10%
End-of-semester exam Exam written 90 min. grades 75%
Lab-Exercises Practical Exercises Evaluation of implementation SW 1-10 grades 10%
Mini Project Project Evaluation of implementation SW 11-14 grades 5%



Legal basis

The module description is part of the legal basis in addition to the general academic regulations. It is binding. During the first week of the semester a written and communicated supplement can specify the module description in more detail.


Course: Microcomputer Systems 2 - Vorlesung
Microcomputer Systems 2 - Vorlesung


  • No module description is available in the system for the cut-off date of 01 August 2099.